The invention relates to semiconductor integrated circuit devices, and specifically to a circuit for improving the speed in which a resistive and capactive conductor, such as the word line in a memory device, can be driven from one voltage to another.
In dynamic random access memories (DRAMs) constructed as generally shown in U.S. Pat. No. 4,081,701 (a 16k bit DRAM) issued to White, McAdams and Redwine and assigned to Texas Instruments, Inc., and in U.S. Pat. No. 4,239,993 (a 64k bit DRAM) issued to McAlexander, White and Rao and assigned to Texas Instruments, Inc. data is stored in a plurality of memory cells arranged in rows and columns, each storage cell consisting of a single capacitor, and the stored data state represented by either the presence or absence of charge stored by the capacitor. Each of the memory cells is connectable to a sense amplifier by means of a transfer gate which connects the storage capacitor to a bit line, with a given column of memory cells is generally associated with a common bit line. A given row of memory cells will be associated with a word line perpendicularly disposed to the bit line, with the word line of the selected row energizing one transfer gate with each bit line, thereby connecting one memory cell to each bit line.
In operation, the first step in the selection of an individual memory cell to which data is to be written, or from which data is to be read, is the selection of the row in which the desired memory cell resides, which is accomplished by presenting a row address in conjunction with a row address strobe signal to the memory device. The row address decoder on the device decodes the row address and, by means of a driver circuit, energizes the word line corresponding to the desired row, which causes each memory cell in the selected row to be connected to a bit line, and thereby sensed by the sense amplifiers. After this sensing, the desired cell is then addressed by presenting a column address to the device, in conjunction with a column address strobe signal, which is similarly decoded to choose the corresponding column. The speed by which a given memory cell may be accessed is determined by the sum of these operations, making it evident that if the time required to energize the cells in a given row increases, the overall time to access a given cell will increase accordingly. It should be noted that each transfer gate of the device presents a capacitive load to the word line driver, and that the word line itself presents a distributed resistance to the word line driver. It should therefore be apparent that the word line driver is driving an R-C load with a voltage step function, making the voltage waveform of a selected word line an exponential having a time constant proportional to the product of the resistance and the capacitance of the word line. Therefore, since it is desired that the word line drivers energize the transfer gates associated with the selected row as quickly as possible, it is desired that the resistance and capacitance which comprise the electrical load of the word line be minimized.
However, as the capacity of DRAM devices increases, certain factors tend to increase the load on the word line drivers of such devices, thereby tending to lengthen the time required in accessing a particular memory cell. As the capacity of such memory devices has increased, the number of rows and columns of memory cells has of course increased. However, since the sensing operation also serves to refresh the memory cells of the selected row in a DRAM, DRAM users prefer that the number of rows in succeeding generations of DRAMs remain the same, in order to keep constant the amount of overhead time required to periodically refresh the DRAM device. For example, a 64k bit DRAM generally contains 256 rows and 256 columns, while a 256k bit DRAM also generally contains 256 rows, but with 1024 columns in order to acheive the 256k bit capacity. Similarly, 1M bit DRAM devices are expected to contain 512 rows, but with 2048 columns, with the refresh period double that of the 256k DRAM. Therefore, as the capacity of memory devices increases, the number of transfer gates which a word line is required to drive is increasing at even a faster rate, as is the the capacitive load of the word lines. In addition, as the capacity of the memory devices increase, it is highly desirable that the surface area of the semiconductor decrease on a a per-memory-cell basis. A large factor in the surface area required for a given memory capacity is the width of the word line; therefore, it is desirable that the word line become as narrow as possible. It is well known that the resistance of a conductor is inversely proportional to its cross-sectional area, so that as the word line is narrowed, its resistance is increased accordingly, which further inreases the loading of the word line drivers as the memory capacity increases.
It is therefore an object of this invention to provide a pull-up circuit, at the end of the word line opposite the driver, which serves to minimize the time required to energize the word line.
It is another object of this invention to provide such a pull-up circuit which efficiently utilizes surface area on the semiconductor device, by sharing portions of the pull-up circuit among a plurality of word lines.
It is another object of this invention to provide a pull-up circuit which provides the above benefits and which serves to keep at a non-energized state those word lines associated with rows which are not selected.
Other benefits and advantages of the subject invention will become apparent after consideration of the description of the preferred embodiments contained herein.